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Position: Front End Infrastructure Engineer (Austin, TX)

Job Overview:
We are seeking an experienced Front-End (FE) Infrastructure Engineer to join our engineering team. In this role, you will be responsible for developing, supporting, and optimizing Front-End Design Verification (DV) flows and CAD infrastructure for complex, large-scale semiconductor projects. You will collaborate closely with verification, RTL, and CAD teams to improve automation, enhance regression management, and ensure the reliability and scalability of verification environments.

The ideal candidate will have deep expertise in FE verification methodologies, regression management, EDA tools, and version control systems, along with experience working directly with EDA vendors to resolve complex technical challenges.

This is a W2 contract position and is not eligible for C2C or W2 referral candidates.

Key Responsibilities: 
Front-End Verification Flow Development
• Design, develop, maintain, and enhance scalable Front-End Design Verification (DV) flows and CAD infrastructure.
• Improve verification methodologies to increase efficiency, robustness, and automation across development teams.
• Develop and support advanced flow-based regression tools while ensuring long-term maintainability.
• Continuously evaluate and implement improvements to verification workflows and infrastructure.
Regression Management & Debugging
• Manage and maintain regression systems supporting complex verification environments.
• Perform regression triage by identifying, debugging, and resolving verification failures.
• Investigate coverage issues, regression failures, and flow stability concerns to minimize development delays.
• Partner with verification engineers to resolve tool and infrastructure-related challenges.
EDA Tool Support & Vendor Collaboration
• Serve as the primary technical resource for Synopsys VCS-related issues, including debugging and advanced troubleshooting.
• Collaborate directly with Synopsys and other Electronic Design Automation (EDA) vendors to resolve escalated technical issues.
• Evaluate new tool capabilities and recommend improvements to verification infrastructure.
• Maintain strong relationships with EDA vendors to ensure optimal tool performance and support.
RTL Architecture & Infrastructure Support
• Deploy, integrate, and maintain RTL architecture tools within Front-End verification environments.
• Ensure seamless integration between RTL architecture tools and verification flows.
• Provide ongoing support and troubleshooting for RTL infrastructure and tool environments.
Version Control & Configuration Management
• Support and maintain version control workflows using Git, Perforce, and Git-P4.
• Develop and improve configuration management processes to support collaborative engineering environments.
• Promote best practices for source code management, branching strategies, and workflow automation.

Required
• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical discipline with 10+ years of relevant experience; or
• Master's degree with 8+ years of relevant experience; or
• PhD with 6+ years of relevant experience.
• Extensive experience designing, maintaining, and troubleshooting Front-End Design Verification (DV) flows and CAD infrastructure.
• Strong expertise in regression management, regression debugging, and coverage analysis.
• Hands-on experience with Synopsys VCS and Cadence IES (Incisive Enterprise Simulator).
• Experience configuring and supporting xprop functionality within VCS and IES environments.
• Advanced knowledge of Git, Perforce, and Git-P4 version control systems.
• Experience deploying and supporting RTL architecture tools.
• Proven ability to troubleshoot complex infrastructure and verification issues.
• Strong analytical, debugging, and problem-solving skills.
• Excellent verbal and written communication skills with experience collaborating directly with EDA vendors.
• Ability to work independently while effectively collaborating within cross-functional engineering teams.
Preferred
• Experience supporting large-scale semiconductor or ASIC/SoC development programs.
• Strong understanding of Front-End verification methodologies and Design Verification best practices.
• Experience developing automation tools and improving engineering workflows.
• Familiarity with scalable verification infrastructure and continuous improvement initiatives.
• Demonstrated ability to lead technical problem-solving efforts across multiple engineering teams.

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Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals Build Careers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture, which is why we offer a benefit package and convenient weekly payment solutions that helps our employees stay healthy and maintain a positive work/life balance. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.