Job Description

Onsite in San Jose, CA 5 days a week.

Description
Architecture and design of high-speed I/O circuit blocks such as TX, PLL, CDR, Analog Front-End (AFE/CTLE), DFE.

QUALIFICATIONS & REQUIRED SKILLS:
Master in Electrical Engineering or more.
Solid background in mixed-signal circuit design, and in particular past experience with PLL, DLL, CDR, DFE, TX, or analog front-end (AFE/CTLE).
Feasibility studies for new interface building-blocks by studying and analyzing existing state-of-the art implementations.
Hands on experience with lab measurement and serial link characterization.
Present architecture and design reviews of key circuits to the rest of the team and counterpart team at headquarters.
Teamwork, dedication, excellent communication skills both written and verbal.