Job Description

Austin, TX or San Jose, CA Onsite  

Description:
Position Requirements:
Role and Responsibilities: Key responsibilities include

Work with architects and designers to build verification environments and test plans
Craft functional verification coverage strategy to ensure complete test suite implementation
Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
Analyze failing tests to root cause along, working with RTL and reference modeling teams
Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
Examine code coverage results, identifying exclusions and improving stimulus
Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics

Skills and Qualifications: Minimum requirements:

BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
Proficient in System Verilog/UVM/OVM, and OOP/C++
Deep understanding of constrained randomization and the development of efficient test suites
Experience with code coverage and functional coverage-driven verification methodology.
Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
Working knowledge of scripting languages such as Python or Perl
Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines

Preferred qualifications:

MS CE/EE with 5+ years of industry experience in verification
Good verbal and written communication skills
Experience of GPU or CPU is a plus

Comments:C3800162